library ieee;
use ieee.std_logic_1164.all;
entity johnson_counter is
port(clk : in std_logic;
reset : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end johnson_counter;
architecture Behavioral of johnson_counter is
signal temp : std_logic_vector(3 downto 0) := (others => '0');
begin
--assign the temparary signal to output port.
--In VHDL-1997, output ports cannot be read. Thats why we use temp here.
count <= temp;
process(clk)
begin
if(rising_edge(clk)) then
if (reset = '1') then ---synchronous reset
temp <= (others => '0');
else
--these are concurrent statements.
--which means they all execute at the same time.
temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= not temp(3);
end if;
end if;
end process;
end Behavioral;